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[Embeded-SCM Develop] vhdlthreelinespi

Description: ＳＰＩ总线与ＣＰＬＤ之间的通信程序，可实现ＳＰＩ串行输入，通过移位寄存器后并行输出-SPI bus and the CPLD communication between these procedures is to realize SPI serial input, through the shift register parallel output after
Platform: | Size: 1024 | Author: 金臻炜 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 用来实现VGA发生时序，显示颜色，用CPLD实现-Used to realize the occurrence VGA timing, display color, with CPLD realize
Platform: | Size: 312320 | Author: | Hits:

[Other] a2d2

Description: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
Platform: | Size: 180224 | Author: | Hits:

[VHDL-FPGA-Verilog] cpld-pwm

Description: 基于cpld的pwm控制设计 采用vhdl.verilog语言设计 对大家比较有用-CPLD-based control design uses the pwm design vhdl.verilog language more useful for everyone
Platform: | Size: 79872 | Author: emily | Hits:

[3G develop] Autostart

Description: 该工具用于使用MAXII CPLD实现了Target I2C功能,例程很全,包括Modelsim仿真-The tool used to realize the MAXII CPLD use Target I2C functions, routines very wide, including ModelSim Simulation
Platform: | Size: 387072 | Author: cathy feng | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 一个关于4CAN卡的硬件程序,用VHDL编写.就是4路CAN总线-4CAN card on the hardware procedures, prepared by VHDL. Is 4 CAN BUS
Platform: | Size: 624640 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 基于CPLD XC95018开发的一段VHDL代码，可实现多个8051单片机互相通讯，对多单片机系统的设计很有参考价值-Based on CPLD XC95018 developed section of VHDL code, can realize more than 8051 mutual communication, single-chip microcomputer system for the design of multi-reference value is
Platform: | Size: 907264 | Author: 蔡彬彬 | Hits:

[VHDL-FPGA-Verilog] cpld-0809

Description: 这是利用VHDL语言编写的关于ADC0809的程序，编的很不错-This is the use of VHDL language on the ADC0809 procedure, made a very good
Platform: | Size: 1024 | Author: 王盗大 | Hits:

[VHDL-FPGA-Verilog] cpld-0832

Description: VHDL语言编写的DAC0832代码，简短而又易懂，可供参考
Platform: | Size: 1024 | Author: 王盗大 | Hits:

[VHDL-FPGA-Verilog] cpld-clock

Description: VHDL语言编写的时钟显示代码，简短而又易懂，个人觉得很不错-VHDL language code of the clock display, the short and easy-to-understand, personal feel very good
Platform: | Size: 1024 | Author: 王盗大 | Hits:

[Com Port] uart

Description: 采用CPLD实现串口通信（Verilog硬件描述语言）-Realize the use of CPLD serial communication (Verilog Hardware Description Language)
Platform: | Size: 5120 | Author: wuzhidong | Hits:

[VHDL-FPGA-Verilog] CpldVhdl

Description: 用VHDL语言写的程序包含如下功能：1.键盘扫描2.控制AD转换3.产生PWM信号与51系列CPU接口，接在51地址数据总线上，单片机通过访问地址总线上的数据寄存器来控制CPLD-VHDL language used to write the procedure that contains the following functions: 1. Keyboard scan 2. Control of AD converters 3. Generate PWM signals with the 51 series CPU interface, and then in the address data bus 51, the single-chip by visiting the address bus data Register to control the CPLD
Platform: | Size: 455680 | Author: liubaogui | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 这是有关VHDL的介绍，随着工业的自动化，CPLD与FPGA被越来越广泛的应用于工业控制领域-This is the introduction of VHDL, with the industrial automation, CPLD and FPGA have been increasingly widely used in the field of industrial control
Platform: | Size: 168960 | Author: liuyong | Hits:

[VHDL-FPGA-Verilog] CPLD-VGA

Description: 有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.
Platform: | Size: 233472 | Author: qqq | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[Embeded-SCM Develop] keyboard

Description: 键盘程序：基于cpld开发环境的4*4键盘程序，很有用哦-Keyboard procedure: CPLD-based development environment 4* 4 keyboard procedures, useful Oh
Platform: | Size: 1024 | Author: xixi | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[Software Engineering] IIC-CPLD

Description: iic总线协议～IIC总线通讯接口器件的CPLD实现，网上下载的资料～～很不错-IIC bus protocol ~ IIC bus communication interface device CPLD realization of downloading the information ~ ~ very good
Platform: | Size: 8192 | Author: allen | Hits:

[Other] Copy-of-I2C-bus-Chinese

Description: I2C中文规范参考资料，CPLD程序设计实现I2C总线-I2C Chinese normative references, CPLD programming realization of I2C bus
Platform: | Size: 782336 | Author: MArtin | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPLD

Description: 项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号，因此硅微谐振式加速度计数据采集电路完成的主要任务是测出两路频率信号的差值。测量要求是：实现10ms内对中心谐振频率为20kHz、标度因数为100Hz/g、量程为±50g、分辨率为1mg的硅微谐振式加速度计输出的频率信号的测量，等效测量误差为±1mg。电路的控制核心为单片机，具有串行接口以便将测量结果传送给PC机从而分析、保存测量结果。 按研究内容设计了软硬件。软件采用多周期同步法实现高精度，快速度的频率测量方案，并使用CPLD编程实现，这也是最难的地方。硬件采用现在流行的3.3V供电系统，选用EPM240T100C5N和较为实用的AVR单片机芯片Atmega64L，对应3.3V供电系统，串行接口使用MAX3232。 最后完成了PCB板的制作，经反复调试后得到了非常好的效果。采集的数据满足项目研究内容中的要求，当提高有源晶振的频率时，精度有大大提高了，此时已远远满足了项目中高精度，快速度测量的要求。另外，采用MFC编程编写了上位机的数据接收和数据处理专用软件，集数据采集，运算，作图，保存功能于一体。 此为CPLD语言部分-err
Platform: | Size: 409600 | Author: tancm | Hits:
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